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Filename Latest commit message Latest commit date
Brage Wiseth 8e46d7e099 _
2026-08-10 10:07:39 +02:00
CPU _ 2026-07-10 17:31:25 +02:00
esp32s3 _ 2026-07-10 17:31:25 +02:00
FPGA _ 2026-07-10 17:31:25 +02:00
scripts _ 2026-07-10 17:31:25 +02:00
stm32g431 _ 2026-08-03 22:11:00 +02:00
.gitignore _ 2026-08-03 22:09:20 +02:00
Makefile _ 2026-07-10 17:31:25 +02:00
README.md _ 2026-08-10 10:07:39 +02:00

RF project

openocd -f interface/ftdi/um232h.cfg -f target/zynq_7000.cfg

if you want to use only FPGA you can load fsbl with bitstream right after if you want only CPU you use the fsbl + application.elf if you want to use both CPU + FPGA you need to use block diagram and connect the fpga design to the processing system and make a special xsa + fsbl with bitstream

PLAN

set up linux / rt linux use scp and ssh to program fpga use mmap or .ko to write drivers for io and fpga io use non propietary tools